Extended Methodology to Determine SRAM Write Margin in Resistance-Dominated Technology Node

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed this article. Increased bitline (BL) resistance sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the ability degraded by an increased leakage current half-selected bitcells on and capacitance operated high frequency. In realistic operation, parasitics also cause 30% SRAM yield loss interconnect resistance-dominated nodes. Thus, method analyzes time-dependent impacts parasitic resistors, capacitors, pass-gate (PG) transistors margin considering negative (NBL) assist technique.